Data registers are typically used to store data for later reading. For example, a “D flip-flop”, also known as a data register, is presented data at the input. The input data is then loaded on the next clock edge, either rising or falling, depending on the type of register, if the clock enable input is true.
A problem exists with the loading and unloading of a register when the input and output of the register are connected to a source and destination, respectively, that are synchronous and of unknown but relatively constant phase to each other.
One solution to this problem is to use a single register. The problem with this approach is that the unload can occur at any time relative to the load. In this case, the register may be loading at exactly the wrong time as the unloading and, therefore, the register output may have corrupt data. This corrupt data may also be both intermittent and persistent.
Adding a second stage register to the output of the first stage register does not fix this problem. The second stage register could also be loaded at the same time. There is a resulting need for a register apparatus loaded synchronously and unloaded out-of-phase with the loading.